library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.cpu_utils.all;

entity mux_8 is
		generic ( 
		size: integer := 32;
		Tpd : Time := unit_delay);
	port (
			in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7 : in bit_vector(size-1 downto 0);
			y : out bit_vector(size-1 downto 0);
			sel : in bit_vector(2 downto 0));
end mux_8;


architecture mux_8_arh of mux_8 is
begin
	with sel select
		y <= in_0 after Tpd when "000",
		in_1 after Tpd when "001", 
		in_2 after Tpd when "010",
		in_3 after Tpd when "011",
		in_4 after Tpd when "100",
		in_5 after Tpd when "101",
		in_6 after Tpd when "110",
		in_7 after Tpd when "111";
end mux_8_arh;